Wafer Level Packaging
Objectifs du cours
Miniaturization of devices always drive engineers and product developers to consider the use of new materials or technologies of assembly. In electronic devices for example, the trend is to make more than Moore's law with 3D integration. In sensors or microfluidics structures, the packaging cost is significant and any effort that can make it smaller and robust at chip level has a positive impact. Wafer scale packaging has benefits that can apply for many other industrial sectors where miniaturization, robustness and large-scale manufacturing are mandatory. The objectives of the course are to give the attendees an overview of what is feasible in terms of packaging at wafer-level. A particular attention will be given to wafer bonding processes, as well as on basic considerations to take at design level in case of connectivity needs. Device validation and testing will also be discussed as these are critical steps to benchmark technologies
Public cible
The course addresses engineers and product developers interested in wafer-level packaging for novel device fabrication, involved in the development of MEMS based products or microtechnology products where wafer processing advanced technology can apply.
Contenu
Day 1
- Introduction and round table
- MEMS & electronic packaging overview
- Wafer processing overview (cleanroom environment, photolithography, CVD, wet and dry etching…)
- Wafer bonding technologies (fusion, anodic, eutectic, solder…)
Day 2
- Connectivity technologies (metallization, TSV, Flip-Chip…)
- Testing and device qualification (functional, mechanical, hermeticity…)
- MEMS sensors examples
- Case discussions
Enseignant(s)
Jean-François Le Néal is a Product Development Freelance at INNOJ.io. After graduating in Mechanical Systems at the University of Technology of Troyes (France), Jean-François worked on Micro & Nano systems as a PhD Student at LAAS-CNRS in Toulouse (France) with an industrial grant from Auxitrol/Esterline Advanced Sensors company. In 2010, he joined Measurement Specialties/TE Connectivity in Bevaix (Switzerland) as a MEMS project engineer. In 2014, he took the position of staff engineer in packaging process engineering. From 2014 to 2021, he took several leadership positions as team leader of the advanced packaging R&D group and Engineering site leader responsible for MEMS, ASIC and packaging integration for state-of-the-art pressure sensors. He is inventor or co-inventor of 10 international patents, most of them directly related to MEMS applications.
| Date et Lieu (jj.mm.aaaa) |
15.01.2025 - 16.01.2025 | Neuchâtel, FSRM |
| Coût (EARLY BIRD) | CHF 1'300.00 |
| Coût | CHF 1'500.00 |
| Langue | English |
| Inscription | Deux semaines avant le cours |
| Organisation | FSRM, Fondation suisse pour la recherche en microtechnique |
| Informations et inscription | Gilles Delachaux, FSRM, e-mail: fsrm@fsrm.ch |
