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Wafer Level Packaging

Course Objectives

Miniaturization of devices always drive engineers and product developers to consider the use of new materials or technologies of assembly. In electronic devices for example, the trend is to make more than Moore's law with 3D integration. In sensors or microfluidics structures, the packaging cost is significant and any effort that can make it smaller and robust at chip level has a positive impact. Wafer scale packaging has benefits that can apply for many other industrial sectors where miniaturization, robustness and large-scale manufacturing are mandatory. The objectives of the course are to give the attendees an overview of what is feasible in terms of packaging at wafer-level. A particular attention will be given to wafer bonding processes, as well as on basic considerations to take at design level in case of connectivity needs. Device validation and testing will also be discussed as these are critical steps to benchmark technologies

Target group

The course addresses engineers and product developers interested in wafer-level packaging for novel device fabrication, involved in the development of MEMS based products or microtechnology products where wafer processing advanced technology can apply.


Day 1

  • Introduction and round table
  • MEMS & electronic packaging overview
  • Wafer processing overview (cleanroom environment, photolithography, CVD, wet and dry etching…)
  • Wafer bonding technologies (fusion, anodic, eutectic, solder…)

Day 2

  • Connectivity technologies (metallization, TSV, Flip-Chip…)
  • Testing and device qualification (functional, mechanical, hermeticity…)
  • MEMS sensors examples
  • Case discussions

Session: 11.12.2023 - 12.12.2023

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2 days


Early bird price : 1'300.00
Normal price : 1'500.00

Course Language



teacher 1

Jean-François Le Néal